There are many applications in which high resolution measurement of a time interval is useful. For example, accurate time interval measurement is often used in various high resolution measurement and instrumentation applications, in analog-to-digital converters based on pulse-width modulation, in phase detectors of digital phase-locked loops, and in mass spectrometer time-of-flight measurements. The industry-wide trend to replace more analog, mixed signal, and radio frequency functionality with increasingly faster digital solutions further enhances the need for high-resolution time measurement.
Time-to-digital converters (TDCs) are often used for such accurate time measurements. The resolution of state of the art in a contemporary 90 nm integrated circuit technology reaches values on the order of picoseconds.
The stop signal of a TDC is typically a periodic reference clock signal that is inevitably disturbed by jitter. If the jitter is on the order of the time resolution of the TDC, or even larger, the effective resolution is thus limited by the clock jitter. It is expected that the resolution may improve with further technology scaling resulting in the reduced gate delays. Unfortunately, clock jitter does not scale with technology. Thus, as the potential resolution of TDCs improves, the relative limiting effect of clock jitter increases.
In principle, it is possible to reduce clock jitter to some extent (although there are limitations because jitter cannot be reduced to zero). However, measures to reduce jitter usually involve a significant amount of added cost, both in terms of integrated circuit area used as well as power consumption. Thus, a more jitter-tolerant TDC may be desirable not only to push the absolute resolution limit of TDCs but also to relax the jitter requirements of the reference clock generator.